The present invention relates to packaging for semiconductors. Recent silicon technology advances have placed increased demand for high density signal routing on organic BGA substrates. Packages with a full area ball array are also being used to reduce the package body size and provide a high input/output (IO) signal density.
Increased signal routing density in the substrate is obtained by using fine pitch vias through the core so that routing layers below the core can be efficiently utilized. The via pitch reduction requires the use of thin core substrates which are susceptible to warpage during thermal excursions. Typically, the regions are under the die corner are regions of stress concentration. Under cycled thermal excursions, cracks can initiate from the ball pad edges and spread into the layers above the ball pad layer. Depending on the design, these cracks may pose a reliability hazard.
Problems exist with the packages which are currently in wide use. Currently, in full array packages, signals are typically routed directly over the ball pads under the die corner on the bottom routing layer. As an example, FIG. 1 shows a typical multi-layer organic BGA flip chip substrate that uses a 9-layer stackup 20 with a thin core. The 9-layer stackup 20 includes a layer L1, a layer L2, a layer L3, a layer L4, a layer L5, a layer L6, a layer L7, a layer L8, and a layer L9. Each of the layers is formed of a conductive material such as copper. Insulative material 21 is provided between each of the conductive layers. An upper protective mask 22 is provided proximate layer L1 and a lower protective layer 24 is provided proximate layer L9. Layer L1 provides a plurality of bump pads 26 (one of which is shown) on which a plurality of solder masses 28 (one of which is shown) are provided. The upper surfaces 28a of the solder masses 28 provide a die site on which the die (not shown) will be placed. A plurality of ball pads 30 (one of which is shown) are provided on Layer L9.
A portion of Layer L9 of the 9-layer stackup 20 is shown in FIG. 2. Circularly shaped ball pads 34 of layer L9 are dispersed throughout layer L9. The ball pads 34 may be dispersed in a partial or full-array format. Placement of a quadrant of the die over the solder masses 28 is represented by line 38. Placement of one of the corners of the die is represented by the point 38a. 
A portion of Layer L8 of the 9-layer stackup 20 is shown in FIG. 3. Layer L8 provides the bottom routing layer. Placement of a quadrant of the die over the solder masses 28 is represented by line 38. Signal traces 36 are dispersed throughout layer L8. Numerous signal traces 36 and other metal structures extend across the layer L8 proximate the die corner 38a. 
The signal traces 36 of layer L8 are routed over the ball pads 34 of layer L9. Areas of high stress are associated with the die corner 38a and in particular the ball pads which are positioned under the area surrounding the die corner 38a. The edges of the ball pads 34 which are associated with the die corner 38a act as stress concentration points and under temperature cycling conditions, cracks are initiated from the edges of the ball pads 34 and extend into the dielectric layer above layer L9. If traces 36 are routed or other metal structures are provided on layer L8 over the ball pads 34 associated with the die corner 38a, the cracks can extend through the traces 36 and cause failures due to trace cracks under cycled stress conditions.
One existing solution to overcoming this problem is to place metal planes on the layer L9 under the die corner 28. A disadvantage of placing metal planes on the layer L9, however, is that it reduces the signal density. Another existing solution to overcoming this problem is to define a circular shaped area with a one (1) millimeter radius using placement of the die corner 38a as the center of the circle. When routing traces on layer L8, traces are not routed within this circular region. A disadvantage of having a one (1) millimeter radius region under the die corner 38a is that it is not sufficient to avoid trace cracks in the layer L8 under temperature cycling conditions for all packaging technolgies.
Therefore, an improved package is needed which will reduce cracks in the signal traces and therefore avoids functional failures caused by stresses under the die corner. The present invention provides such a package. Features and advantages of the present invention will become apparent upon a reading of the attached specification, in combination with a study of the drawings.